COMPANY : CODETECH IT SOLUTION NAME : MRUNALI KALE INTERN ID : CT08JPQ DOMAIN : VLSI DURATION : 4 WEEKS MENTOR : SRAVANI TASK NAME: DESIGN ALU USING VERILOG DESCRIPTION : Step 1: Define the ALU ...

and bitwise NOT. Conclusion : The 4-bit ALU efficiently performs basic arithmetic and logical operations using a combinational circuit. It correctly executes addition, subtraction, AND, OR, and NOT ...