Design-Reuse

Front-end analysis accelerates ASIC flow

The problem for Infrant Technologies, a young network storage IC company, was to figure out how to avoid the typical iterative design scenario. For our latest design, a 250-MHz network storage device ...
Design-Reuse

C based design methodology accelerates ASIC/FPGA design cycles

Electronic Design Automation is largely about saving time in the development of electronic designs. EDA tools strive to reduce verification time, design cycle time, and time to market. EDA is ...
Electronic Design

STARC Certifies MATLAB and Simulink as Preferred Tools in STARCAD-AMS Design Workflow

April 15, 2013. MathWorks has announced that the Semiconductor Technology Academic Research Center (STARC) in Japan has selected and certified MATLAB, Simulink, and Embedded Coder as the preferred ...
EDN

Front-end analysis accelerates ASIC flow

The problem for Infrant Technologies, a young network storage IC company, was to figure out how to avoid the typical iterative design scenario. For our latest design, a 250-MHz network storage device ...